An important trend in development of semiconductor technology is scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) for improving integration level and reducing manufacturing cost. However, it is well known that short channel effects arise as the size of MOSFETs decreases. As the MOSFETs are scaled down, a gate also has a reduced effective length and actually controls fewer charges in a depletion region when a gate voltage is applied. Consequently, a threshold voltage of the MOSFETs drops with a reduced channel length.
Chenming Hu et al. discloses a FinFET formed on a SOI (silicon-on-insulator) substrate in U.S. Pat. No. 6,413,802, which comprises a channel region provided in a central portion of a fin of semiconductive material, and source/drain regions provided at two ends of the fin. A gate electrode is provided at both sides of the channel region and surrounds the latter to provide for example a double-gate FinFET, in which inversion channels are created at both sides of the fin. The channel region in the fin has a small thickness so that the whole channel region is controlled by the gate, which suppresses the short channel effect. Thus, the FinFET is an excellent candidate for the MOSFET which is further scaled down in size.
Both in a double-gate FinFET having a gate over two side surfaces of a fin and in a triple-gate FinFET having a gate over a top surface and two side surfaces of a fin, the gate extends mainly over the two side surfaces of the fin. Consequently, a channel width of the FinFET depends on a height of the fin of the FinFET. However, in conventional FinFETs, the fin is typically formed from a bulk silicon by etching. The height of the fin cannot be well controlled. Variations of the height of the fin in the manufacture process adversely affect properties of the FinFETs.